Power modeling of embedded memories
نویسنده
چکیده
After Moore’s Law the number of transistors on an integrated circuit doubles every 18 months. New circuits are furthermore clocked with increasing frequencies. This development not only leads to an increase of the available functionality, but also to a rise of the electrical power consumption of these systems. The power consumption of integrated circuits is problematic in two respects: on one hand the power must be fed into the system, on the other hand the heat produced on the chip must be dissipated. An increased power consumption consequently leads to reduced battery lifetimes and increased energy costs. Today already 80% of the office related power consumption in the USA stems from computers. The heat development of integrated circuits reduces their reliability and lifetime. The required cooling measures (ceramic packages, heat fins, fans, etc.) furthermore increase the system cost. For the development of low power systems it is necessary to estimate and consider the power consumption already in the early stages of design. For such estimates models of the system blocks are required. This thesis describes a methodology for the generation of models of the power consumption of embedded memories. Memories have a special importance among the system blocks as it is forecast that more than 90% of the area of newly developed systems will be occupied by memory within ten years. In addition to the requirements on models, like accuracy, speed and mathematically closed form the presented approach specifically adresses the requirements on the modeling procedure. These are mainly the protection of intellectual property and low modeling costs. As a key point of the approach a method for the generation of nonlinear (signomial) models from empirical data is presented. This regression based method allows the generation of piecewise model functions, which can be used for optimisation through geometric programs. The presented models reduce the prediction error by up to 95% compared to existing approaches.
منابع مشابه
Embedded Memory Test Strategies and Repair
The demand of self-testing proportionally increases with memory size in System on Chip (SoC). SoC architecture normally occupies the majority of its area by memories. Due to increase in density of embedded memories, there is a need of self-testing mechanism in SoC design. Therefore, this research study focuses on this problem and introduces a smooth solution for self-testing. In the proposed m...
متن کاملLow Power March Memory Test Algorithm for Static Random Access Memories (TECHNICAL NOTE)
Memories are most important building blocks in many digital systems. As the Integrated Circuits requirements are growing, the test circuitry must grow as well. There is a need for more efficient test techniques with low power and high speed. Many Memory Built in Self-Test techniques have been proposed to test memories. Compared with combinational and sequential circuits memory testing utilizes ...
متن کاملModeling and Performance Evaluation of Multi-Processors Organization with Shared Memories
This paper is primarily concerned with theoretical evaluation of the performance of multiprocessors system. A markovian waiting line model has been developed for various different multi-processors configurations, with shared memory. The system is analysed at the request level rather than job level.
متن کاملSynthesis of Application-Speci c Memories for Power Optimization in Em bedded Systems
This paper presents a novel approach to memory power optimization for embedded systems based on the exploitation of data locality. Locations with highest access frequency are mapped onto a small, low-power application-speci c memory which is placed close the processor. Although, in principle, a cache may be used to implement such a memory, more e cient solutions may be adopted. We propose an ar...
متن کاملModeling storage and retrieval of memories in the brain
We have proposed a neural network model that stores the incoming information after orthogonalizing it in the same manner as vectors are orthogonalized. The scheme enables the brain to compare a new informational system with those in the memory and store its similarities and differences with the old memories in an economical manner. This allows the brain to have an enormous capacity and yet the ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2003